A technique disclosed in the present invention relates to semiconductor devices including a high dielectric constant (high-k) gate dielectric film, and especially a gate dielectric film that is made of hafnium oxide or zirconia oxide, or silicon oxide containing hafnium oxide and zirconia oxide, and manufacturing methods of the same.
An increase in gate capacity per unit area, that is, a further reduction in thickness of a gate dielectric film, is required in order to reduce power consumption and increase performance of 32-nm generation complementary metal oxide semiconductor (CMOS) devices. However, using conventional silicon oxide film materials for the gate dielectric film increases a leakage current, which results from a reduction in thickness, to an unacceptable level. Thus, techniques of using for the gate dielectric film a high-k dielectric film having a higher relative dielectric constant than that of the conventional silicon oxide film materials have been developed. A HfSiON film that is thermally stable at 1,000° C. or higher and has a relative dielectric constant of 13 or more is one of the most promising candidates for the material of the high-k dielectric film. However, in conventional structures using the HfSiON film as a gate dielectric film and using polysilicon gate electrodes, an increase in threshold voltage due to Fermi level pinning cannot be ignored in addition to an increase in equivalent oxide thickness (EOT) due to depletion, especially in P-type metal-insulator-semiconductor (MIS) transistors.
Gate stack techniques using metal gate electrodes, instead of the polysilicon gate electrodes, have been remarkably developed in order to address these problems. In the case of using metal gates for bulk CMOS devices, a metal having an effective work function (eWF) close to the conduction band of silicon (Si) must be selected for n-type MIS transistors, and a metal having an eWF close to the valence band of Si must be selected for p-type MIS transistors. Specifically, a metal having an effective work function of 4.8 eV or more needs to be selected for the p-type MOS transistors, and a metal having an effective work function of 4.3 eV or less needs to be selected for the n-type MIS transistors.
General relations between metal materials and their work functions show that metal materials such as titanium (Ti), molybdenum (Mo), or tantalum (Ta) are candidate for the n-type MIS transistors, and metal materials such as platinum (Pt), ruthenium oxide (RuO2), or titanium nitride (TiN) are candidate for the p-type MIS transistors. Thus, it is desirable to configure a dual metal gate process by selecting the above materials as the metal gates of the p-type MIS transistors and the metal gates of the n-type MIS transistors.
However, the candidate n-type materials described above (Ti, Mo, Ta) have many integration problems, such as difficulty of etching and cleaning, and unstable characteristics with elevated thermal budget (up to 700 C).
On the other hand, another method has been proposed to obtain a desired work function as n-type MIS transistors without using the above metal materials as a metal gate material of the n-type MIS transistors. That is, a method has been proposed to include a metal capable of changing a work function to that of the n-type MIS transistor, such as lanthanum (La), Dysprosium, (Dy), Erbium (Er), or Gadolinium (Gd), in, e.g., a gate dielectric film, or to insert this metal between the metal gate and the gate dielectric film. For example, in the structure in which this metal is inserted between the metal gate and the gate dielectric film, a desired work function can be obtained using candidate metal materials of the n-type MIS transistors. As a result, a desired transistor threshold voltage as the n-type MIS transistors can be obtained (e.g., see Japanese Published Patent Application No. 2007-324594).